Anna University Examination May/June 2012

Important Questions

Common To

EE46:Digital Logic Circuits

EC1261A Digital Logic Circuits

080280029:Digital Logic Circuits

131405:Digital Logic Circuits

10133EE406A:Digital Logic Circuits

Note: These are only Important questions , These Question May Or May Not be Asked for University Examination

Unit I

1. Obtain the minimum SOP using Quine McCluskey’s method and verify using K – Map.

F = m

_{0}_{+}m_{2 }+ m_{4 }+ m_{8 }+ m_{9 }+ m_{10 }+ m_{11}+ m_{12 }+ m_{13}2. Determine the prime implicants of the following function using tabulation method and verify using K –Map. F = (A,B,C,D) = ∑ (3,4,5,7,9,13,14,15)

3. Design a Binary to BCD code converter and BCD to Excess -3 code converter.

4. Reduce the given expressions using Boolean algebra:

(1) x’y’z’ + x’y’z + x’yz + xy’z + xyz

(2) p’q’r + p’qr’ + p’qr + pqr’ + pq’r’

5. Design a decimal adder to add two decimal digits.

Unit II

1. Design a asynchronous decade counter using JK flipflop.

2. Design a 8 X1 Mux using 2 X1 multiplexers.

3. Design a synchronous counter using JK flipflop in the sequence 7,4,3,1,5,0,7….

4. Draw and explain the block diagram of Mealy circuit

5. Design a MOD -5 synchronous counter using JK flip-flops .Draw a timing diagram.

6. Design a 2 bit Magnitude Comparator.

Unit III

1. Describe the steps involved in design of asynchronous sequential circuit in detail with an example.

2. Explain the working of a 3 – input TTL totem-pole NAND gate.

3. Explain the concept and implementation of ECL logic family.

4. Explain In detail about FPGA.

5. A combinational circuit is defined by the functions .

F

_{1 }(A,B,C ) =∑ (3,5,6,7) F

_{2 }(A,B,C ) =∑ (0,2,4,7).Implement the circuit with PLAUnit IV

1. Design an asynchronous sequential circuit that has two inputs X

_{2}and X_{1}and one output Z. When X

_{1}= 0, that output Z is 0. The first change in X_{2 }that occurs while X1 is 1 will cause output Z to be 1. The output Z will remain 1 until X_{1}returns to 0.2. An asynchronous sequential circuit has two internal states and one output. The excitation and

output functions describing the circuit are

Y

_{1 }= x_{1}x_{2 }+ x_{1}y’_{2 }+ x’_{2}y_{1}Y

_{2 }= x_{2 }+ x_{1}y’_{1}y_{2 }+ x’_{1}y_{1}Z = x

_{2 }+ y_{1}a) Draw the logic diagram of the circuit.

b) Derive the transition table and output map.

c) Obtain a flow table for the circuit.

3. The Circuit has two inputs T (toggle) and C (clock) and one output Q. The output state is complemented if T=1 and clock C changes from 1 to 0 otherwise, under any other input condition, the output Q remains unchanged. Derive the primitive flow table and implication table and the logic diagram.

4. Draw the State diagram and obtain the primitive flow table for a circuit with two inputs X

_{1}and X_{2 }and two outputs Z_{1}and Z_{2 }that satisfies the following conditions.1) When X

_{1 }X_{2}=00, output Z_{1}Z_{2 }=00.2) When X

_{1 }= 1 and X_{2}change from 0 to 1, the output Z_{1}Z_{2 }=01.3) When X2 = 1 and X

_{1 }change from 0 to 1, output_{ }Z_{1}Z_{2 }=10.4) Otherwise output does not change.

5. Implement the following Boolean functions with a PLA.

F

_{1}(A, B, C) = ∑ (0, 1, 2, 4) F

_{2}(A, B, C) = ∑ (0, 5, 6, 7) F

_{3}(A, B, C) = ∑ (0, 3, 5, 7)Unit V

1. Write VHDL program for 4x1 multiplexer.

2. Explain in detail the design procedure for register transfer language.

3. Write an HDL behavioral description of JK flip-flop using if-else statement based on the value of present state.

4. Write VHDL program for 4-bit ripple counter.

5. Explain the design procedure of RTL using VHDL