Saturday, April 14, 2012

INTIMATION TO ANNA UNIVERSITY STUDENTS REGARDING APRIL/MAY 2012 EXAMINATION(ONLY FOR STUDENTS ADMITTED IN THE YEAR (2001 - 2006))





ANNA UNIVERSITY
CHENNAI - 600 025
Office of the Controller of Examinations

NOTIFICATION(12.04.2012 - THURSDAY)

In view of the fact that there are no regular students of Anna University, Chennai admitted in the year 2001 to 2006 in the colleges situated under Zone VII to XVII (Salem, Coimbatore, Erode, Trichy, Karaikudi, Dindigul, Tirunelveli & Nagercoil) and only a few candidates from these colleges will be appearing for their arrear papers under Anna University, Chennai, it is decided to limit the Examination Centres for April/May 2012 examinations in these Zones. Accordingly, the details of Examination Centres and group of colleges attached to
each centre are given in the Annexure.

1.        Candidates from these colleges have to write the Theory Examination, only at the designated Examination Centre.

2.       However, Practical Examination will be conducted at the respective college where the candidate has undergone the course of study.

3.       Hall Ticket will be issued and have to be collected only from the Principal of the college where the candidate studied last.

4.       Results and Statement of Marks will be sent to the Principal of the college where the candidate last studied

5.       For any clarification, contact the respective Principal or C20/C30/C70/C80 section in Office of the Controller of Examinations in Phone Nos. 22357244, 22357263, 22357286 & 22357288.

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List of Exam Centres for April/May 2012 Theory Examinations
(Salem,Coimbatore,Tirchy,Karaikudi,Tirunelveli Region Colleges)
(Only For Students Who Admitted In the Year 2001 -2006 and Got Arrears still )


source: annauniv.edu

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EE 2354 MICROPROCESSORS AND MICROCONTROLLER NOV/DEC 2011 ANNA UNIVERSITY QUESTION PAPER


B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.
Sixth Semester
Electrical and Electronics Engineering
EE 2354 — MICROPROCESSORS AND MICROCONTROLLER
(Regulation 2008)
Time : Three hours                                                                                     Maximum : 100 marks
Answer ALL questions.
PART A — (10 × 2 = 20 marks)

1. Draw the schematic of latching low-order address bus in 8085 microprocessor.
2. If the stack segment register contains 3000h and stack pointer register contains 8434h, what is the physical address of the top of the stack in 8086 microprocessor?
3. Why do we need look-up table?
4. How are the 8085 instructions classified according to the functional categories?
5. Draw the 'Mode Word' format of 8251 USART.
6. State the use of ISR and PR registers in 8259 PIC.
7. List the on-chip peripherals of 8051 microcontroller.
8. What are the addressing modes of 8051 microcontroller?
9. Why do we need opto-isolator circuit between microcontroller and the Stepper motor?
10. Mention the I/O instructions of 8051 microcontroller.

PART B — (5 × 16 = 80 marks)

11. (a) (i) Explain in detail the 8085 interrupt structure. (8)
(ii) Draw the timing diagram for IN and OUT instruction of 8085 and explain. (8)
Or
(b) (i) Draw the internal block diagram of 8086 and explain the bus interface unit and execution unit. (8)
(ii) How address decoding is done in memory Interface. (8)

12. (a) (i) Write a program to count from 0 to 9 with one second delay between each count. At the count of 9, the counter should reset itself to 0 and repeat the sequence continuously. Assume the clock frequency is 1 MHz. (8)
(ii) Write a program with a flowchart to multiply two 8-bit numbers.(8)
Or


(b) (i) Compare the similarities and differences of CALL and RET instructions with PUSH and POP instructions. (8)       
(ii) Sixteen bytes are stored in memory locations at XX50h to XX5Fh. Transfer the entire block of data to new memory locations starting at XX70h. (8)

13. (a) (i) Explain the operating modes of 8255 programmable peripheral interface. (8)
(ii) Draw the logical block diagram of 8279 keyboard display controller and explain. (8)
Or
(b) (i) Draw the control word of 8253 timer/counter and explain the operating modes of 8253 timer/counter. (8)           
(ii) Why do we need A/D converter and D/A converter? Draw the block diagram to interface 8085 microprocessor with A/D convertor and D/A convertor. (8)

14. (a) (i) Explain the program memory and data memory structure of 8051 microcontroller. (8)
(ii) Draw the pin diagram of 8051 microcontroller and explain its port structure. (8)
     Or
(b) (i) Draw the TMOD register format and explain the different operating modes of timer in 8051 microcontroller. (8)
(ii) Explain how serial communication is performed in 8051 microcontroller. (8)

15. (a) (i) Explain with a program to rotate the stepper motor in both clockwise and anticlockwise direction using 8051 microcontroller. (8)
(ii) How to interface a 7 segment display using 8051 microcontroller. (8)
Or
(b) (i) How 8051 is used in washing machine control? (8)
(ii) How do you interface a 4 × 4 matrix keyboard using 8051 microcontroller? (8)

EC2354 VLSI DESIGN ANNA UNIVERSITY NOV/DEC 2011 PREVIOUS SEMESTER QUESTION PAPER


B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.
Sixth Semester
Electronics and Communication Engineering
EC 2354 — VLSI DESIGN
(Regulation 2008)
(Common to PTEC 2354 – VLSI Design for B.E. (Part-Time) Fifth Semester
Electronics and Communication Engineering, Regulation 2009)
Time : Three hours                                                                                        Maximum : 100 marks
Answer ALL questions.
PART A — (10 × 2 = 20 marks)
1. Determine whether an NMOS transistor with a threshold voltage of 0.7 V is operating in the saturation region if GS V = 2 V and =DS V 3V.
2. Write down the equation for describing the channel length modulation effect in NMOS transistors.
3. Write the expressions for the logical effort and parasitic delay of n input NOR gate.
4. Why does interconnect increase the circuit delay?
5. Draw a pseudo NMOS inverter.
6. What are the advantages of differential flip flops?
7. State the objective of functionality test.
8. What are the test fixtures required to test a chip?
9. Write the Verilog module for an half adder.
10. What are the delay specifications available in Verilog HDL for modeling a
logic gate?
PART B — (5 × 16 = 80 marks)
11. (a) (i) An NMOS transistor has the following parameters : gate oxide thickness = 10 nm, relative permittivity of gate oxide = 3.9, electron mobility = 520 2 cm /V-sec, threshold voltage = 0.7 V, permittivity of free space = 14 10 85 . 8 − × F/cm and (W/L) = 8. Calculate the drain current when ( GS V = 2 V and = DS V 1.2 V) and ( GS V = 2 V and = DS V 2 V) and also compute the gate oxide capacitance per unit area. Note that W and L refer to the width and length of the channel respectively. (3 + 3 +
(ii) Draw and explain the DC and transfer characteristics of a CMOS inverter with necessary conditions for the different regions of operation. (8)
Or
(b) (i) Explain the gate, source/drain formation and isolation steps of CMOS fabrication process with neat diagrams. (8)
(ii) Give a brief note on the different process techniques to enhance the performance of CMOS transistors. (8)           

12. (a) (i) Explain the static and dynamic power dissipation in CMOS circuits with necessary diagrams and expressions. (10)
(ii) Discuss the principle of constant field scaling and also write its effect on device characteristics . (6)
Or
(b) (i) Explain the different reliability problems related to the design of reliable CMOS chips. (10)
(ii) Give a brief account on design margin. (6)



13. (a) (i) Describe the basic principle of operation of dynamic CMOS, domino and NP domino logic with neat diagrams (12)
(ii) Write the basic principle of low power logic design (4)
Or
 (b) (i) Compare the sequencing in traditional domino and skew tolerant domino circuits with neat diagrams. (8)
(ii) Explain the problem of metastability with neat diagrams and expressions. (8)

14. (a) Explain the manufacturing test principles in detail. (16)
Or
(b) Describe the adhoc testing and scan based approaches to design for testability in detail. (16)      

15. (a) (i) Draw the three input CMOS NOR and NAND gates and write the Verilog switch level modeling for both. (10)
(ii) Explain the continuous and implicit continuous assignment with two suitable examples for each. (6)
Or
(b) (i) Draw the logic diagram of 4 to 1 MUX using NAND gates and write the gate level modeling using Verilog HDL. (8)
(ii) Give a brief note on the looping statements available in Verilog HDL and write a verilog code for D Latch. (6 + 2)    

IT2351 NETWORK PROGRAMMING AND MANAGEMENT NOV/DEC 2011 ANNA UNIVERSITY QUESTION PAPER


B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.
Seventh Semester
Computer Science and Engineering
IT 2351 — NETWORK PROGRAMMING AND MANAGEMENT
(Common to Sixth Semester – Information Technology)
(Regulation 2008)

Time : Three hours                                                                                       Maximum : 100 marks
Answer ALL questions.
PART A — (10 × 2 = 20 marks)
1. What is Socket?
2. Define well-known port.
3. List the steps to create TCP echo server.
4. List the exceptions in Select function.
5. Describe SO_KEEPALIVE.
6. What are the alternatives for DNS?
7. Define mutex.
8. List any two differences between ping and trace route program.
9. State the goal of RMON.
10. What are the key capabilities of SNMP?
PART B — (5 × 16 = 80 marks)
11. (a) Draw a TCP socket flow diagram and explain the functions. (16)
Or
(b) Explain the following in detail :
(i) Iterative server (8)
(ii) Concurrent server. (8)

12. (a) Write down the Pseudo code for TCP echo Server and echo Client. (16)
Or
(b) Briefly describe the following :




(i) Server process crashes (4)
(ii) Server host crashes (4)
(iii) Server host crashes and reboots (4)
(iv) Server shutdown. (4)

13. (a) Write down the program for UDP echo Server and echo Client. (16)
Or
(b) Describe the functions and main components of DNS. (16)

14. (a) Explain IPv4 and IPv6 interpretability with neat sketch. (16)
Or
(b) Explain the implementation of a trace route program in detail. (16)

15. (a) Explain the SNMPV1 protocol and the practical issue in detail. (16)
Or
(b) Define and explain MIB-II in detail. (16)

ANNA UNIVERSITY JUNE 2012 RESULTS | AU JUNE 2012 RESULTS ANNOUNCING DATE(TENTATIVE) | ANNA UNIVERSITY SECOND/FOURTH/SIXTH/EIGHT SEMESTER JUNE 2012 RESULTS | WHEN WILL THE JUNE 2012 RESULTS WILL BE ANNOUNCED


Information Regarding Anna University, Chennai (Common To All Colleges In Tamilnadu) June/July 2012 Results

After A Long Duration In Years (Say 3 To 4 ) Anna University, Chennai Taken Charge To Conduct University Examinations For All College Students Who Are Admitted In The Colleges Affiliated To Anna University During  June/July 2012  (Second,Third,Fourth Year) And June/July 2012(First Year). After So May Confusion In Timetable and Exam schedule the Examination has been completed as follow

First Year Students:

Second Semester June/July 2012 Examinations For First Year Students Including Arrear Will End With 29.06.2012

Second Year And Third Year Students

Fourth Semester May/June 2012 Examinations For Second Year Students Will End With 29.05.2012

Sixth Semester May/June 2012 Examinations For Third Year Students Will End With 15.06.2012 

Final Year Students

Eight Semester May/June 2012 Examinations For Final Year Students Will End With 06.06.2012

So Now The Questions Among The Students Is When Will Anna University Publish The 2nd,4th,6th Semester May/June 2012 Results
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ANNA UNIVERSITY,CHENNAI RESULTS FOR ANNA UNIVERSITY BE/BTECH EIGHT SEMESTER (FINAL YEAR) MAY/JUNE 2012 ARE EXPECTED TO ANNOUNCE BY LAST  WEEK OF JUNE 2012

ANNA UNIVERSITY,CHENNAI RESULTS FOR ANNA UNIVERSITY BE/BTECH FOURTH,SIXTH SEMESTER MAY/JUNE 2012 ARE EXPECTED TO ANNOUNCE BY LAST WEEK JULY 2012 OR FIRST WEEK OF AUGUST 2012 [Tentative]
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ANNA UNIVERSITY MAY/JUNE 2012 RESULTS | AU MAY/JUNE 2012 RESULTS ANNOUNCING DATE(TENTATIVE) | ANNA UNIVERSITY SECOND/FOURTH/SIXTH/EIGHTH SEMESTER APRIL/MAY 2012 RESULTS | WHEN WILL THE ANNA UNIVERSITY MAY/JUNE 2012 RESULTS WILL BE ANNOUNCED

This Thread Gives All Latest Official And Unofficial Information Regarding Anna University, Chennai,Coimbatore,Madurai,Tirchy,Tirunelveli(Now Its Has Been Merged and Called Anna University,Chennai) May/June 2012 Results (Common To All Colleges In Tamilnadu) 

After A Long Duration In Years (Say 3 To 4 ) Anna University, Chennai Taken Charge To Conduct University Examinations For All College Students Who Are Admitted In The Colleges Affiliated To Anna University During May/June 2012 Session (Second,Third,Fourth Year) And June/July 2012(First Year). After So Many Confusions In Timetable and Exam schedules the Examination Yet To complete By Second Week Of July 2012 Month(The Overall Examinations Schedule)
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Latest Update On 2nd,4th,6th,8th Semester Anna University May/June 2012 Results

Paper Valuation For 4TH Semester,6TH Semester Has been already Over, 8th Semester Results For Students Who Got Arrears in Lower Semesters will be also published along with 2nd,4th,6th semester results
Latest News From Trusted Sources 18/08/2012 At 11.00 Pm:
ANNA UNIVERSITY,CHENNAI MAY/JUNE 2012 RESULTS HAS BEEN ANNOUNCED BY 18.08.2012 @ 11 pm
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ANNA UNIVERSITY GRADE SYSTEM:
RESULTS HAS BEEN ANNOUNCED BY 11 PM TODAY(18.08.2012)

RESULTS LINK1 (ANNA UNIVERSITY,CHENNAI/MADURAI) : CLICKHERE
ENTER REGISTER NUMBER
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RESULTS LINK1 (ANNA UNIVERSITY,COIMBATORE) : CLICKHERE
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RESULTS LINK1 (ANNA UNIVERSITY,TIRCHY/TIRUNELVELI) : CLICKHERE
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ANNA UNIVERSITY MARK SYSTEM:
RESULTS LINK1 (ANNA UNIVERSITY) : CLICKHERE
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April/may 2012 anna university results, anna university results April/may 2012, anna university results 2012, 2012 april anna university results, au april/may 2012 results,april/may 2012 au results ,results announcing date,anna university may/june 2012 results, fourth semester results 2012,sixth semester april/may 2012 results,eight semester april/may 2012 results , anna univ results 2012,may/june 2012 anna university fourth,second,sixth semester results, anna univ june 2012 results, results 2012 anna university, 2nd, 4th,6th,8th semester results announced , final year april/may 2012 results,june 2012 results,april/may/june 2012 results,anna univ april/may 2012 results announcing date,april/may 2012 second semester results, april/may 2012 fourth semester results, april/may 2012 sixth semester results, april/may 2012 eight semester results,au results 2012, anna university Chennai,tirunelveli,Coimbatore,tirchy,Madurai april/may/june 2012 results

ANNA UNIVERSITY APRIL/MAY 2012 RESULTS | AU APRIL/MAY 2012 RESULTS ANNOUNCING DATE(TENTATIVE) | ANNA UNIVERSITY SECOND/FOURTH/SIXTH/EIGHT SEMESTER APRIL/MAY 2012 RESULTS | WHEN WILL THE APRIL/MAY 2012 RESULTS WILL BE ANNOUNCED

Information Regarding Anna University, Chennai (Common To All Colleges In Tamilnadu) May/June 2012 Results

After A Long Duration In Years (Say 3 To 4 ) Anna University, Chennai Taken Charge To Conduct University Examinations For All College Students Who Are Admitted In The Colleges Affiliated To Anna University During April/May 2012 (Second,Third,Fourth Year) And June/July 2012(First Year). After So May Confusion In Timetable and Exam schedule the Examination has been completed as follow

First Year Students:

Second Semester June/July 2012 Examinations For First Year Students Including Arrear Will End With 29.06.2012

Second Year And Third Year Students

Fourth Semester April/May 2012 Examinations For Second Year Students Will End With 29.05.2012

Sixth Semester April/May 2012 Examinations For Third Year Students Will End With 15.06.2012 

Final Year Students

Eight Semester April/May 2012 Examinations For Final Year Students Will End With 06.06.2012

So Now The Questions Among The Students Is When Will Anna University Publish The 2nd,4th,6th Semester May/June 2012 Results
---------------------------------------------------------------------------------
ANNA UNIVERSITY,CHENNAI RESULTS FOR ANNA UNIVERSITY BE/BTECH EIGHT SEMESTER (FINAL YEAR) MAY/JUNE 2012 ARE EXPECTED TO ANNOUNCE BY LAST  WEEK OF JUNE 2012

ANNA UNIVERSITY,CHENNAI RESULTS FOR ANNA UNIVERSITY BE/BTECH FOURTH,SIXTH SEMESTER MAY/JUNE 2012 ARE EXPECTED TO ANNOUNCE BY LAST WEEK JULY 2012 OR FIRST WEEK OF AUGUST 2012 [Tentative]
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