Friday, August 10, 2012

HIGH SPEED NETWORKS MODEL QUESTION PAPER ANNA UNIVERSITY


B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.
Seventh Semester
Electronics and Communication Engineering
CS2060 — HIGH SPEED NETWORKS
(Regulation 2008)
Time : Three hours Maximum : 100 marks
Answer ALL questions.
PART A — (10 × 2 = 20 marks)
1. List and explain the types of frame relay messages.
2. Give some examples of ATM applications.
3. State the key characteristics to be considered for deriving the analytic
equations for the queuing model.
4. What are meant by choke packets?
5. What is meant by a credit allocation scheme?
6. List and explain the mechanism available for supporting rate guarantees
in an ATM GFR service.
7. List some requirements for inelastic traffic.
8. State and explain the types of PHBs for differentiated services.
9. List the various reservation attributes and styles of the RSV Protocol in
detail.
10. What is meant be traffic engineering?
PART B — (5 × 16 = 80 marks)
11. (a) (i) With a neat sketch explain the various fields of an ATM cell. (10)
(ii) Discuss the various non real time ATM services. (6)
Or
(b) (i) Explain the fiber channel protocol architecture in detail. (8)
(ii) Give the requirements of wireless LAN in detail. (8)
12. (a) (i) Describe the single server queuing model with its structures
and parameters. (10)
(ii) Explain the Kendall’s notation and the common distributions
for the queuing model. (6)


Or
(b) (i) Explain in detail the explicit and implicit congestion signaling.(8)
(ii) List and explain the frame relay congestion control techniques.(8)
13. (a) (i) Describe the TCP implementation policy details. (8)
(ii) List and explain the categories of switch algorithms used for ATM congestion control and fair capacity allocation. (8)
Or
(b) Discuss in detail the ways in which TCP deals with the calculation of retransmission timers. (16)
14. (a) (i) Explain the Integrated services architecture and the QoS support functions. (8)
(ii) List and explain the various categories of Integrated services Architecture. (8)
Or
(b) Explain the Random Early Detection. (16)
15. (a) Explain the design goals and characteristics of the Resource reservation protocol in detail. (16)
Or
(b) Explain the RTProtocol architecture and draw its header format. (16)


EE2302 ELECTRICAL MACHINES — II PREVIOUS YEAR NOV/DEC 2011 QUESTION PAPER ANNA UNIVERSITY


B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.
Fifth Semester
Electrical and Electronics Engineering
EE 2302 — ELECTRICAL MACHINES — II
(Regulation 2008)
Time : Three hours Maximum : 100 marks
Answer ALL questions.
PART A — (10 × 2 = 20 marks)
1. What do you mean by single layer and double layer winding?
2. What are the various function of damper winding provided with alternator?
3. What is a synchronous capacitor?
4. What are V–curves?
5. Why are the rotor slots of a 3 phase induction motors skewed?
6. Define slip of induction motor.
7. State the effect of rotor resistance on starting torque.
8. What are the various method of speed control of 3 phase induction motor?
9. What type of motor is used for ceiling fan?
10. State the application of shaded pole motor.
PART B — (5 × 16 = 80 marks)
11. (a) (i) Derive from first principle, the EMF of 3 phase alternator. (8)
(ii) The following open circuit and short circuit test are made on a 6000 kVA, 6600 V, star connected, 2 pole, 60 Hz turbine driven alternator. If I = 125 A, at open circuit terminal voltage = 8200 V. With armature short circuited I = 125 A. IL = 800 A (line). At the rated load and upf armature loss is 1.5% of out put. Determine the percentage regulation at rated load and 0.8 p.f. lag. (8)
Or
(b) (i) Explain how will you determine the d and q axis reactance of a synchronous machine in your laboratory. (8)
(ii) For the salient synchronous machine, derive the expression for power developed as a function of load angle. (8)
12. (a) Explain V–curve and inverted V curve. (16)
Or
(b) Explain effect of changing field current excitation at constant load. (16)
13. (a) (i) Explain with neat sketches the principle of a 3 Phase induction motor. (8)
(ii) A 6 pole, 50 Hz, 3-Phase, induction motor running on full load develops a useful torque of 160 N m. When the rotor emf makes 120 complete cycle per minute. Calculate the shaft power input. If the mechanical torque lost in friction and that for core loss is 10 N m, complete.
(1) The copper loss in the rotor windings.
(2) The input the motor.
(3) The efficiency.
The total stator loss in given to be 800 W. (8)
Or
(b) (i) Explain top slip characteristic of 3 phase induction motor. (8)
(ii) Develop the equivalent circuit for a 3 phase induction motor. (8)
14. (a) Describe with a neat sketch, the principle and working of a star delta starter and autotransformer starter of a 3 phase induction motor. (16)
Or
(b) Explain, with a neat sketch, slip power recovery scheme of 3 phase induction motor. (16)
15. (a) Explain with a neat diagram the following types of single phase induction motor.
(i) Split phase induction run motor.
(ii) Capacitor start induction run motor, and also draw the slip torque characteristics. (16)
Or
(b) Describe the constructional features & principle of operation of hysterisis motor and AC Series motor. (16)

COMPUTER ARCHITECTURE AND ORGANIZATION EC2303 ANNA UNIVERSITY PREVIOUS YEAR/MODEL QUESTION PAPER ECE DEPARTMENT


B.E./B.Tech DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.
Fifth Semester
Electronics and Communication Engineering
EC 2303 — COMPUTER ARCHITECTURE AND ORGANIZATION
(Common to Sixth Semester Biomedical Engineering)
(Regulation 2008)
(Common to PTEC 2303 – Computer Architecture and Organization for B.E.
(Part-time) Electronics and Communication Engineering
Fourth Semester Regulation – 2009)
Time : Three hours Maximum : 100 marks
Answer ALL questions.
PART A — (10 × 2 = 20 marks)
1. Define priority encoder.
2. What are the factors to be considered in selecting a number representation
to be used in a computer?
3. Write down the equation for carry generate and propagate.
4. Define coprocessor.
5. Compare the two methods to design the hardwired controller.
6. What is the use of micro assembler?
7. What is DRO and NDRO?
8. What is temporal locality?
9. What are the limitations of programmed IO?
10. Write down the CPU steps to determine the status of IO device.
PART B — (5 × 16 = 80 marks)
11. (a) (i) Draw the block diagram of a 4 bit register level magnitude comparator and explain. (8)
(ii) Briefly explain the organization of IAS computer with its instruction set. (8)
Or
(b) (i) How does one detect and correct errors during data transmission ? (8)


(ii) Describe in detail the different kinds of addressing mode with an example. (8)
12. (a) Explain 2’s complement multiplier with a neat block diagram. (16)
Or
(b) Explain floating point adder pipeline with neat block diagram. (16)
13. (a) (i) Write short notes on Nano programming. (8)
(ii) Describe the characteristics of supper scalar processing. (8)
Or
(b) Design a micro programmed control unit of non-pipelined general purpose computers (16)
14. (a) Describe in detail magnetic tape memories and disk memories. (16)
Or
(b) Describe cache memory in detail. (16)
15. (a) (i) What is DMA? Draw the block diagram and explain it in detail.(8)
(ii) Describe vectored interrupt scheme with a neat block diagram.(8)
Or
(b) (i) Define fault tolerance. How is it related to redundancy? Explain different approaches for designing fault tolerance systems. (8)
(ii) Explain different types of bus arbitration scheme. (8)

SYSTEM SOFTWARE CS2304 ANNA UNIVERSITY NOV/DEC 2011 PREVIOUS YEAR QUESTION PAPER


B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.
Fifth Semester
Computer Science and Engineering
CS 2304 — SYSTEM SOFTWARE
(Common to Information Technology)
(Regulation 2008)
Time : Three hours Maximum : 100 marks
Answer ALL questions.
PART A — (10 × 2 = 20 marks)
1. Define system software.
2. Write the abbreviation for the following :
(a) SIC (b) XE (c) CISC (d) RISC.
3. Distinguish assembler and interpreter.
4. What do you mean by literal?
5. What are the functions of loader and linker?
6. Define relocation.
7. Write any two basic macroprocessor functions.
8. Briefly write about MASM macro processor.
9. Define text editor
10. What do you mean by debugger?
PART B — (5 × 16 = 80 marks)
11. (a) Explain the SIC machine architecture in detail.
Or
(b) Describe the following in VAX architecture
(i) Memory
(ii) Registers
(iii) Data formats
(iv) Instruction formats
(v) Addressing modes
(vi) Instruction set and
(vii) Input/output.
12. (a) Discuss in detail the assembler design options.
Or
(b) Explain machine dependent assembler features in detail.
13. (a) Describe machine dependent loader features in detail.
Or
(b) Explain the following in detail :
(i) Linkage editor
(ii) Dynamic linking
(iii) Bootstrap loaders.
14. (a) Explain the features of machine independent macro processor in
detail.
Or
(b) Describe the following in detail :
(i) Conditional macro expansion


(ii) MASM macro processor
(iii) ANSI C macro language.
15. (a) Explain the editor structure with neat diagram.
Or
(b) Discuss interactive debugging systems in detail.