EC6302 Digital Electronics Syllabus Notes Question Papers 2 Marks with Answers Question Bank with answers Anna University EC6302 DE Notes Syllabus 2 Marks with answers ECE 3rd Semester - Regulation 2013 3rd Semester Syllabus Notes

Anna University EC6302 Digital Electronics Notes Syllabus 2 marks with answers Part A Question Bank with answers Key - ECE 3rd Semester

Anna University EC6302 Digital Electronics Syllabus Notes 2 marks with answer is provided below. EC6302 Notes Syllabus all 5 units notes are uploaded here. here EC6302 DE Syllabus notes download link is provided and students can download the EC6302 Syllabus and Lecture Notes and can make use of it.

EC6302 DIGITAL ELECTRONICS SYLLABUS REGULATION 2013

UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES
Minimization Techniques: Boolean postulates and laws – De-Morgan‟s Theorem - Principle of Duality - Boolean expression - Minimization of Boolean expressions –– Minterm – Maxterm - Sum of Products (SOP) – Product of Sums (POS) – Karnaugh map Minimization – Don‟t care conditions – Quine - Mc Cluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive–OR and Exclusive–NOR Implementations of Logic Functions using gates, NAND–NOR implementations – Multilevel gate implementations- Multi output gate implementations. TTL and CMOS Logic and their characteristics – Tristate gates

UNIT II COMBINATIONAL CIRCUITS
Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor – Parallel binary adder, parallel binary Subtractor – Fast Adder - Carry Look Ahead adder – Serial Adder/Subtractor - BCD adder – Binary Multiplier – Binary Divider - Multiplexer/ Demultiplexer – decoder - encoder – parity checker – parity generators – code converters - Magnitude Comparator.

UNIT III SEQUENTIAL CIRCUITS
Latches, Flip-flops - SR, JK, D, T, and Master-Slave – Characteristic table and equation –Application table – Edge triggering – Level Triggering – Realization of one flip flop using other flip flops – serial adder/subtractor- Asynchronous Ripple or serial counter – Asynchronous Up/Down counter - Synchronous counters – Synchronous Up/Down counters – Programmable counters – Design of Synchronous counters: state diagram- State table –State minimization –State assignment - Excitation table and maps-Circuit implementation - Modulo–n counter, Registers – shift registers - Universal shift registers – Shift register counters – Ring counter – Shift counters - Sequence generators.

UNIT IV MEMORY DEVICES
Classification of memories – ROM - ROM organization - PROM – EPROM – EEPROM –EAPROM, RAM – RAM organization – Write operation – Read operation – Memory cycle - Timing wave forms – Memory decoding – memory expansion – Static RAM Cell- Bipolar RAM cell – MOSFET RAM cell – Dynamic RAM cell –Programmable Logic Devices – Programmable Logic Array (PLA) - Programmable Array Logic (PAL) – Field Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using ROM, PLA, PAL

UNIT V SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS
Synchronous Sequential Circuits: General Model – Classification – Design – Use of Algorithmic State Machine – Analysis of Synchronous Sequential Circuits Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode circuits – Incompletely specified State Machines – Problems in Asynchronous Circuits – Design of Hazard Free Switching circuits. Design of Combinational and Sequential circuits using VERILOG.

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