EC2353 Antenna and Wave Propagation Question Papers EC2353 AWP Question Papers Anna University ECE 6th Semester Question Papers

EC2353 Antenna and Wave Propagation Question Papers EC2353 AWP Question Papers Anna University ECE Question Papers 6th Semester download
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EC2353 Antenna and Wave Propagation Question Papers EC2353 AWP Question Papers Anna University ECE 6th Semester Question Papers Reviewed by Anirudhan R on 6:38 AM Rating: 5

1 comment:

  1. B.E./B.Tech. DEGREE EXAMINATION, MAY/JUNE 2012
    Sixth Semester
    Electronics and Communication Engineering
    EC 2354/EC 64 – VLSI DESIGN
    (common to PTEC 2354 – VLSI DESIGN for B.E. (part – time) fifth semester –
    electronics and communication engineering regulation 2009 )
    (regulation 2008)
    TIME : THREE HOURS MAX:100 MARKS
    ANSWER ALL QUESTIONS
    PART-A (10 X 2 = 20)
    1. DRAW THE IV CHARACTERISTICS OF MOS TRANSISTOR.
    2. BREIF THE DIFFERENT OPERATING REGIONS OF MOS SYSTEM.
    3. DRAW THE EQUIVALENT CIRCUIT STRUCTURE OF LEVEL 1 MOSFET MODEL
    IN SPICE.
    4. BRIEF ABOUT THE VARIATION OF FRINGING FIELD FACTOR WITH THE
    INTERCONNECT GEOMETRY.
    5. COMPARE CMOS COMBINATIONAL LOGIC GATES WITH REFERENCE TO THE
    EQUIVALENT N-MOS DEPLETION LOAD LOGIC WITH REFERENCE TO THE
    AREA REQUIREMENT.
    6. WHAT ARE THE ADVANTAGE OF USING A PSEUDO N-MOS GATE INSTEAD
    OF A FULL CMOS GATE
    7. WHAT ARE THE FACTORS THAT CAUSE TIMING FAILURES?
    8. WHAT ARE THE ADVANTAGE OF A SINGLE STUCK AT FAULT?
    9. WITH COMPONENT INSTANTITATION, WRITE A VHDL PROGRAM FOR A
    BUFFER.
    10. WRITE A NOTE ON TRANSPORT DELAY
    PART-B (10 X 2 = 20)
    11. (a) DISCUSS IN DETAIL ABOUT:
    (1) FULL-CUSTOM MASK LAYOUT DESIGN (8)
    (2) CMOS INVERTER LAYOUT DESIGN (8)
    [OR]
    (b) (I) WITH A NEAT DIAGRAM DISCUSS IN DETAIL ABOUT DC TRANSFER
    CHARACTERISTICS OF CMOS. (8)
    (II) WRITE A SHORT NOTES ON THE FOLLOWING ALONG WITH THE MASK
    VIEW
    (i) OXIDE RELATED CAPACITANCE (4)
    (i i) JUNCTION CAPACITANCE (4)
    12. (a) (i) OBTAIN AN EXPRESSION FOR LEVEL 2 MODEL EQUATION OF MOSFET
    IN SPICE. (8)
    (i i) DISCUSS IN DETAIL ABOUT:
    (1) VARIATION OF MOBILITY WITH ELECTRIC FIELD.
    (2) VARIATION OF CHANNEL LENGTH IN SATURATION MODES.
    (3) SATURATION OF CARRIER VELOCITY. (8)
    [OR]
    (b)(i) HOW DO THE SPICE MOSFET MODEL ACCOUNT FOR THE PARASITIC
    DEVICE CAPACITANCES?(8)
    (i i) EXPLAIN THE CHARECTERIZATION OF CIRCUITS.(8)
    13. (a) (i)FOR A TWO INPUT NAND GATE DERIVE AN EXPRESSION FOR THE DRAIN
    CURRENT. (8)
    (ii) DRAW A CMOS NOR2 GATE AND ITS COMPLEMENTARY OPERATION
    WITH NECESSARY EQUATIONS. (4)
    (ii i) OBTAIN A CMOS LOGIC DESIGN REALIZING THE BOOLEAN FUNCTION
    Z=A(D+E)+BC (BAR) (8)
    [OR]
    (b) (i) DRAW A CIRCUIT DIAGRAM OF THE CMOS SR LATCH AND EXPLAIN
    IN DETAIL. (8)
    (ii) ALONG WITH THE NECESSARY INPUT AND OUTPUT WAVEFORMS
    OF THE CMOS DFF NEGATIVE EDGE TRIGGERED MASTER SLAVE D FLIP
    FLOP. (8)
    14. (a) (i) EXPLAIN INDETAIL ABOUT PARTITION AND MUX TESTING WITH
    NECESSARY EXAMPLE AND DIAGRAM. (8)
    (ii) EXPLAIN THE PRINCIPLE OF SILICON DEBUG. (8)
    [OR]
    (b) (i) ELABORATE THE SCAN BASED TECHNIQUES. (8)
    (ii) DISCUSS IN DETAIL ABOUT:
    (I) PSEUDO RANDOM PATTERN GENERATOR. (4)
    (II) OUTPUT RESPONSE ANALYSER. (4)
    15. (a) USING MIXED LEVEL MODE WRITE A VHDL PROGRAM FOR A
    (i) COMPARATOR. (8)
    (ii) D –FLIP FLOP. (8)
    [OR]
    (b) WITH ALL THE THREE TYPES OF MODELING WRITE A VHDL
    PROGRAM FOR A
    (i) DECODER (8)
    (ii) FULL ADDER. (8)

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